As is known, the performance of power vertical-conduction MISFET devices (or more simply vertical MISFETs), in particular, vertical-current-flow DMOS transistors (VDMOS devices), may be affected by the presence of parasitic components, which may produce variable effects according to the operating conditions. For example, VDMOS devices may comprise body regions, having a conductivity, housed at a short distance from one another in an epitaxial layer having opposite conductivity. Adjacent body regions and the portion of the epitaxial layer comprised therebetween consequently define a parasitic JFET, which is activated when the VDMOS device is conducting.
Besides depending upon the operating conditions and the level of doping of the epitaxial layer, the resistance of the parasitic JFET may depend basically upon its channel width, i.e., upon the distance between the body regions. In practice, the greater the distance between the body regions, the lower the resistance of the JFET, and vice versa. On the other hand, overlying the portion of epitaxial layer forming the channel of the JFET are gate electrodes, normally made of polysilicon, which are insulated only through e.g., a gate-oxide layer, and remain capacitively coupled. The effect of the capacitive coupling, however, increases as the distance between the body regions increases, unlike the resistance of the parasitic JFET. Consequently, it may not be possible to act on this distance to reduce the resistance of the parasitic JFET, without penalizing the dynamic characteristics of the VDMOS device. Furthermore, the increase of the distance between the body regions may also be in conflict with the need to reduce the dimensions of the devices, which has acquired an increasingly greater importance in modern microelectronics.
Different measures have been proposed to overcome the above drawbacks.
A first measure envisages an enrichment implant to increase the doping in a surface layer of the wafer housing the VDMOS device so as to increase the conductivity. Alternatively, the enrichment may be obtained by epitaxially growing a layer having an appropriate doping level. In some cases, however, and especially for low-voltage devices, the maximum doping of the body regions differs only a little from the doping of the epitaxial layer. The surface enrichment that extends throughout the entire wafer may thus interfere significantly with the threshold voltage and the length of the VDMOS channel (which extends in the proximity of the surface of the body regions) up to the point where functionality of the device is jeopardized (premature punch-through). For this reason, the surface enrichment is normally selectively performed, for example with masked implants, and confined to portions of the epitaxial layer comprised between the body regions and arranged at a slight distance from the latter.
A further measure to improve the dynamic performance regards the use of gate-oxide layers with differentiated thicknesses. More precisely, localized growths of oxide are performed, normally by LOCOS technique, above the areas forming the channel of the parasitic JFET, which may possibly be enriched. The LOCOS technique, however, is rather imprecise, because of the characteristic “birdbeaks” that insinuate laterally in a way that may be only roughly foreseen. The reduction in the dimensions may not, therefore, be pushed beyond a still somewhat unsatisfactory limit.
Other techniques envisage the deposition of oxide instead of using the LOCOS growth technique. Also in this case, however, there may be limits that prevent a significant reduction in the dimensions from being achieved. In particular, parts of the wafer are freed from the deposited oxide, which instead remains above the parasitic JFETs. For this purpose, the oxide is deposited on a previously shaped polysilicon layer, which defines gate electrodes and, moreover, functions as a mask. The areas that are to remain covered by the oxide are located under first openings of the mask, which have dimensions such as to be completely filled on account of the fact that the oxide is conformally deposited also on the vertical walls, thus increasing in thickness in a horizontal direction. The areas where the oxide is to be completely removed are located, instead, under second openings of the mask, which have dimensions such as not to be filled completely. The oxide is then etched to remove a controlled thickness in such a way as to free the second openings, but not the first openings. The second openings, therefore, have dimensions in a pre-determined ratio with the first openings or larger, because otherwise they not could be freed of the oxide. This constraint may limit the density of integration that can be obtained.
Furthermore, the polysilicon layer used as mask also forms the gate electrode, but is interrupted by the first and second openings. Consequently, the resistance offered by the gate electrode may not be optimal.